SAI VIDYA INSTITUTE OF TECHNOLOGY
Department of Computer Science and Engineering
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Tuesday, October 3, 2017

MODULE 3 (first half) NOTES

Analog and Digital Electronics October 03, 2017 1 comment :
MODULE 3 (first half) NOTES

SYLLABUS: 
  • Multiplexers
  • De-multiplexers
  • 1 of 16 Decoders
  • BCD to Decimal Decoders
  • Seven Segment Decoders
  • Encoders
  • Exclusive-OR gates
  • Parity Generator and Checkers
  • Magnitude Comparator
  • PAL and PLA
  • HDL implementation of Data Processing Circuits
  • Arithmetic Logic Circuits and ALU



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